In order to enhance the resolution of an LCD such as the thin film transistor type, i.e., TFT-LCD, it is required to increase the frequency of the data clock signal used in the drive IC for the LCD. However, this is limited by the charging characteristics of the LCD and the drive IC. Alternatively, there has been proposed other systems to enhance the resolution without increasing the frequency of the data clock, which includes a n-pixel/1-clock pulse system for driving n pixels per 1 clock pulse and a dual scan system for scanning the screen simultaneously with two lines. Meanwhile, it is also required to make the frame memory have the responsive speed of at least 160 MHz and the storage capacity of 3.9 Mytes to obtain the display resolution of SXGA (super extended graphics array) order, for example, 1280.times.1024. Nevertheless, the responsive speed of the conventional frame memory is limited to 50 MHz.
Referring to FIG. 1, there are shown a plurality of frame memory blocks and multiplexers constituting a conventional interface for communicating R (Red) video data to the TFT-LCD of the dual scan system. In operation, the input video signal is firstly stored into the frame memories 11 to 18, and then divided into an upper side image part and a lower side image part applied to the TFTLCD (not shown). During this application, it is necessary to consider the responsive speed of the drive IC (integrated circuit) of the LCD and the gate pulse duration required for sufficiently charging the liquid crystals. In this case, the conventional interface requires 24 frame memories to process a least number of video data by dividing the frequency of the video signal by four and dual scanning according to Equation 1, as follows: EQU 24=4 (frequency dividing).times.2(Dual Scan).times.3(RGB 3 Colors) (1)
In this case, each frame memory requires the storage capacity of 167 KBytes. Since the memories commercially available have the storage capacities of 130, 260, 330 or 520 KBytes, the memory with the storage capacity of 260 KBytes may be used as the frame memory. Hence, if the 24 frame memories each having 260 KBytes are used to constitute the total storage capacity to process the video data, there occurs a memory loss of 2.4 MBytes which is the difference between the required storage capacity 3.9 MBytes and the total storage capacity 6.3 MBytes.
Other known systems to drive a dual scan LCD, incorporated herein by reference, are exemplified by U.S. Pat. No. 5,387,923 to Phillip E. Mattison, et al. entitled VGA Controller UsingAddress Translation To Drive A Dual Scan LCD Panel And Method Therefor; U.S. Pat. No. 5,537,128 to David Keene, et al. entitled Shared Memory For Split-Panel LCD Display Systems; and U.S. Pat. No. 5,617,113 to Dennis W. Prince entitled Memory Configuration For Display Information.